In recent years, the development trend of electronic semiconductors, miniaturization, high efficiency, low consumption and low cost are continuously pursued. Through Silicon Via (TSV) is to drill a via on a wafer or a chip by a laser, and then to fill the hole with a conductive material to form a conductive path, thereby vertically connecting the upper and lower surfaces of the wafer, enabling the stacking multiple chips. This technique is called a three-dimensional integrated circuit (3D IC) package. Compared with the conventional multi-chip package, a three-dimensional package can shorten the signal transmission path by staking a plurality of chips, so that the signal is transmitted more quickly, and the space occupied by the package is also reduced. These advantages have allowed 3D IC to become a competing technology for the semiconductor manufacturers, and to become a key to maintaining competitiveness in integrated circuit production and the packaging/testing industry.
Taiwan semiconductor manufacturers, such as TSMC, ASE, SPIL, POWERTECH, etc., have all actively built 2.5D and 3D IC packaging and testing capacity in recent years. In addition, other semiconductor manufacturers, such as Samsung, Elpida, and Intel have similarly put resources into the research and production of 3D IC. 3D IC products are expected to become mainstream electronic goods in the next generation.
In 3D IC packaging technologies, silicon chips are stacked and connected vertically, which can significantly reduce the size of component, enhance efficiency, reduce energy consumption, and improve functionality. The TSV interconnection is a core technology in 3D IC, its critical processes involve wafer thinning, TSV formation, and Cu-to-Cu connections. The Cu-to-Cu connection can be achieved by direct diffusion bonding or micro-bump bonding. The former does not need any foreign filler material, so pure Cu contacts can be formed. However, a high processing temperature (usually requiring 300° C. or higher) and a large processing pressure (25 bars or more) must be provided to drive the diffusion of Cu atoms. In addition, pretreatment processes upon the surface of Cu substrates are often required to activate the bonding surfaces. These complex procedures and precautions make the direct diffusion bonding a relatively costly and complicated process. In addition, the required high pressure is not only costly, but may cause damages to the electronic components on the wafer. On the other hand, micro-bump bonding involves soldering process, i.e., molten solders wet the substrates and solidified, to form electronic interconnections, and therefore does not require the pre-treatments and the high processing pressure. However, solders are commonly composed of tin (Sn), which can readily react with the Cu metal as the substrates to produce a large fraction of brittle and electrical resistant intermetallic compound (IMC) formation in the contacts, thereby significantly reducing the reliability of the contacts.
It is therefore necessary to provide an electric connection and a method of manufacturing the electric connection for providing a Cu-to-Cu connection with high reliability, in order to solve the problems existing in the conventional technology as described above.